tlb compares the memory latency for two different pointer chains. The two chains occupy the same amount of cache space, but they stress the memory subsystem differently. The first chain accesses one word per page, while the second chain randomly jumps through all the lines on a page before jumping to the next page. When all of the pointers reside in the cache (which is the usual case), and all of the pages for the first chain reside in the TLB, then the average memory latencies should be identical. Assuming there is a fixed size TLB, then at some point the number of pages accessed by the first page will be larger than the TLB. At this point the average latency for each memory access for the first chain will be a cache hit plus some fraction of a TLB miss.
Once the TLB boundary is located tlb reports the TLB miss latency as the TLB latency for twice as many pages as the TLB can hold.
Comments, suggestions, and bug reports are always welcome.
Table of Contents